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For Task 3, we had to build a circuit that adds two user-determined 4-bit binary numbers. Instead of a counter, the idea was to use 4 switches to control each bit of a 4-bit number. There would be 8 switches in total that would be used, the first four for the first addend and the next four for the second addend. The screen would display the sum in hexadecimal, on two seven-segment screens, much like the way the numbers showed up in Task 2. I started off having 8 inputs, connected to the adding driver I made in VHDL (called "P2Part3driver" here). The adder takes all of the inputs, adds them, and puts the first four (right to left) bits into the displaying driver. The most significant bit, result[4], goes through an AND gate (which was done to assign it to a new variable), then goes through the displaying driver. Both seven-segment displays then work together to show the result of adding any 4-bit binary numbers in hexadecimal.  

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The image of my circuits is shown below:

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I also did the first extension for this lab, which was to make the whole first circuit in a block diagram file, without using VHDL to control which inputs made which segments true, like before. This means that I had to find the boolean expression for each output using the original truth table I had used for determining when a segment should be true and by making Karnaugh maps. In this extension, I learned that I could make a shortcut for when a variable was not true; I put the original (ex: q[0]) through a not gate, then called it not[name of letter I associated it with] (ex: "nota"). After all 7 maps were done, I made a counter, which took two inputs, as usual: a clock and a reset button. I had trouble when trying the circuit on the breadboard, and noticed it started from 0000 then went to 1000, then 0100, then 1100, etc. which was in the reverse order from what it should have been. This led to me making a "reverser" VHDL file, which takes in 4 bits, and assigns to the output each bit of the input, but in the reverse order (so input(3) becomes output(0), for example). The output of the reverser is q[3..0], which is the correct order to count up in, then gets put into all of the gates, and goes through them to the 7 outputs. The picture of this circuit is below (please note that there are twice as many outputs here and that the output of the reverser is unlabeled).

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In this project, I learned about how to represent circuits in VHDL and a lot about how counters work. I also became more familiar with hexadecimal notation and with solving problems through building drivers.