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For this project, we made a more complex version of the light display from Project 4. While Project 4 took only 3 bits of instructions, this takes 10. The first two bits specify the kind of instruction: 00 for move, 01 for operation, 10 for branch, and 11 for conditional branch. Within each kind of instruction, the rest of the bits hold different values that also will depend on what numbers they are assigned in the instruction register. The provided chart is shown below:

Opcode

Format

Description

00

[C1 C0] [Dest1 Dest0] [Src1 Src0] [Val3 Val2 Val1 Val0]

Move from 
SRC to DEST

 

Dest10: 00 = ACC, 01 = LR, 10 = ACC low 4 bits, 11 = ACC high 4 bits

 

 

Src10: 00 = ACC, 01 = LR, 10 = IR low 4 bits sign extended, 11 = all 1s

 

01

[C1 C0] [Op2 Op1 Op0] [Src1 Src0] [Dest0] [Val1 Val0]

Binary operator
DEST = DEST op SRC

 

Op210: 000 = add, 001 = sub, 010 = shift left, 011 = shift right maintain sign bit

 

 

Op210: 100 = xor, 101 = and, 110 = rotate left, 111 = rotate right

 

 

Src10: 00 = ACC, 01 = LR, 10 = IR low 2 bits sign extended, 11 = all 1s

 

 

Dest0: 0 = ACC, 1 = LR

 

10

[C1 C0] [U3 U2 U1 U0] [Addr3 Addr2 Addr1 Addr0]

Branch to ADDR

11

[C1 C0] [Src0] [U2 U1 U0] [Addr3 Addr2 Addr1 Addr0]

Branch to ADDR if SRC is 0

 

Src0: 0 = ACC, 1 = LR

With these instructions, we were able to implement loops, as well. 

The first task was to create a new vhdl project in quarts called pld2--mine, however, is called Project5. After that, task 2 called for a ROM (read-only memory) called pldrom, which is where I stored the instructions for Project5 to interpret. Pldrom has two signals: addr (address; the position we are at when counting up) and data, which is where the instructions are stored. I mapped those into Project5 afterwards. 

Task 3 was to create the skeleton of the top level (Project5/pld2) file. Important to note is that the file now has not one, but rather two, execute states, so that the first execute state can be used to assign sources and the second execute state can assign the destinations. The first is more about storing values while the second execute state is about manipulating those stored values. Notice that since the branch instructions don't need destinations, they also don't need to do anything in sExecute2. The flow of the execution is always going from sFetch to sExecute1 to sExecute2, as one can see in the picture below.


The black lines are the places that correspond to checking and carrying out the corresponding instructions based on the additional info rows in the table. Under the first line, for example, the source is checked, and if it is 00, the source will be assigned ACC, and so on.

Task 4 was to format the first execute state. This meant that I had to assign the corresponding bits of IR that would indicate where to look for what kind of info (source, destination, etc.) to the things the instructions dictated for them. For instance, when the case of IR (9 down 8) is 00, we are in the move case, and within the move case, the source is found in IR(5 down 4), so we look within that to decide what to assign to where.

In task 5, I had to do the same thing with the second execute state--tell it where to look for what and what to do with what it found. In the move and binary operation cases, it checked the destinations and assigned them things based on the source values. The operations were also listed here, such as xor, adding, shifting, etc. The branching instructions don't need any more information so they don't do anything here, which is why I used "null" as a way to pass through those instructions and do nothing. 

For task 6, we just needed to test if our file worked in gtkwave. The picture of my simulation is below. The instruction register's hex value equivalents of their 10-digit binary is shown in the second row, and the 8-bit converted to hex is under it, representing which lights are turned on. The running of programs on the circuit board after was much easier to interpret, however.


Task 7 was to write such a program and run it on the circuit board. The program was supposed to load 16 into the light register, make it count down to 0, then make it flash from all 1's to all 0's 8 times. A picture of my instructions is below. 

Task 8 was to make two more programs. For my first, I made a program that displays all 1's, then all 0's, then changes between 10101010 and 01010101 7 times. My instructions and a video of the program are shown below:


21653483.480p.mp4

My other program counts up to 4, shifts left 5 times, and leaves that bit sitting there until after the program returns to start and starts shifting after reaching 4 again. My code for the program is shown below.


I did extension 4, which was to make a freeze/pause button. Upon being pressed and released, the program will stop moving forward. After being pressed again, it will resume as usual from where it left off. If reset is hit, it will be un-paused, as well. To add the ability to pause, I made an input at the beginning of Project5 for the pause button, called "pause", which keeps track of the state of the button, as well as an internal value called "paused," which keeps track of whether or not the counter is paused. I added the pause button into the clock process after the main one, then added in various lines of code to account for the pause button. On reset, for example, paused equals 1, which represents not being paused, while 0 represents being paused. The elif case checks what the state of paused is, and always returns the opposite, meaning that pressing it will either pause or unpause it depending on the current state. When the clock counts up, we also have to make sure that when the paused case is true (so 0), the counter will not progress any further, while if it is off (so 1), it will proceed as usual. My code and video are below.

 
pausevid.mp4

This project taught me a lot about how to check and categorize bits from the instruction register and how to control the data flow through the states. I also learned about the null function and was able to solve problems involving making the LR follow certain patterns while before this was very difficult for me to comprehend. 

Thanks to: Professor Maxwell, Professor Taylor, Melody, Arthur

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