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For this project, the assignment was to make a circuit in VHDL that would create a state machine that tests the user's reaction time.

After making a new subdirectory for my project and copying over files like the 7-segment display file, which I would reuse, I created a VHDL file to make the timer I would use as a symbol file in my block diagram file. 

To make the VHDL driver, I first inserted a Moore state machine template, then added inputs and outputs. We needed a reset button, a start button, and a "react" button as inputs, and the green and red LEDS and the two seven-segment displays as the outputs. An internal counter was also needed, used to count up and to make the process wait. The logic of the state machine was as follows: starting the machine from an idle state, the user hits the start button, then the red LED lights up. The user then hits the react button after the clock starts ticking and the green LED lights up (if they hit it while the red LED is still on, it will result in a "failure" and the game will go back to being idle), and the second they hit it, the timer stops and the light goes off. Also note that hitting the reset button any time will return the state to idle. A picture of the process is below. I also added conditional statements to the end of the file to tell the LEDs when to light up as well as how to make the clock work. 

To make the counter keep adding to its count, I made count have one bit added to it for every time nothing was pressed ("else"). 
Next, I made the top-level file, the BDF, to implement the timer. A picture of this is shown below:

First, there needs to be 4 buttons taken as input. They all go into the timer driver, and are converted into three kinds of outputs: green LED, red LED, and 8-bit "time". The LEDs go directly to outputs linked to those places on the board, while the two halves of the counter time are linked to two seven-segment displays (seven parts/outputs to each).

I did extension 5, which was to turn the system into a two-player game to see who reacted faster. I needed another 7-segment display to show a "1" if player 1 won and a "2" if player 2 did. When the score was either cleared or the game had just initialized, I also had to keep it at a default, so in total, this meant that the input needed to have 2 bits so it could fit 3 possibilities. The results correspond to displaying a 1, a 2, and an 8; when the result index is 1, it means the corresponding segment is turned off. The driver for displaying the winner is shown below:

"ShowWinner" was therefore an output of the [adjusted] timer VHDL file. Depending on what the program outputs, the ShowWinner will go through to the winnerdisp driver to create either a 1, a 2, or an 8. I also needed a new input, the button for player 2 to press. To incorporate this, I needed to add more states to take into account which person (player 1 or player 2) hit their button first. If it was player 1, for example, the state would be "sP1win" and the counter would keep advancing unless player 2's button was pressed, upon which it would not only enter the idle state, but also assign the value "01" (translated to "1" on the seven segment display through the aforementioned new seven segment display) to showWinner. This would effectively show the winner's number next to the score, and when reset was pressed, it would also disappear and turn the display back to showing an "8". The picture below showcases the new states.

The top-level BDF for this extension was similar to the last, except there were extra outputs for the additional display, another input button, and a new plugin for the new output showWinner to go through. This is shown below:
Here is a video of me testing the extension:


When player one hits the button first, "1" is displayed in the third 7-segment display, and the same applies for when player two hits the reaction button first.

This project taught me a lot about how state machines work, as well as how to use VHDL and state logic in conjunction with Quartus to pass along information through the machines. I had more experience working with VHDL and felt a lot more comfortable using it than last time. 

Helped by: Kellan

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