For this week's [very long] project, we built a CPU using the provided CPU design template. The CPU imported data from a ROM, a RAM, and an ALU.
Tasks 1-3 were to make a project in quartus, then download the provided MIF files for the ROM and RAM. This was done in the same manner as in the last project.
Task 4 defined the signals that we had to use in our top level file, which I called "Project7", in accordance with my "Project#" theme. We wanted a clock, a reset button, and all the register outputs to be included so we could see them in the gtkwaves to come. We also needed to make port map statements and such for the ROM and RAM.
Task 5 was to make an ALU using the provided template. The ALU needed 4 signals: the first and second operands, the operation-specifying input, the condition register output, and the actual output value/result of the operation. We needed to define what to do for each operation, and since one condition was asking if there was a carried one, we needed to use 17 bits to get the answer, then map the low 16 bits to the actual answer that would be the output. We pretended like we used 16 the whole time; the sole purpose of the 17th bit was to see if there was a carried one for the condition checks at the bottom of the file. The condition register has 4 bits, and bit index 0 would be 1 if all zeroes in the result was true, for example. The gtkwave for the ALU is shown below:
The last task was to make the fibonacci sequence as a gtkwave simulation. This meant making an MIF file to give instructions, which was fairly straightforward (except the part where I spent literally 9 hours trying to find my mistake, which turned out to be a colon instead of a semicolon in my MIF...). My logic for this is shown below:
As you can see, I use RA and RB as the indicators for what I want to add. RC is the counter that has RD (which is always 1) subtracted from it each round in the loop, meaning it goes from 10 to 0, and when it's 0, the loop stops, which is how we get the first ten numbers only. The loop is to have the sum of RA and RB get put into RE, then output unless RC reaches 0. Then, RB is passed on to RA and RE is passed on to RB, which, when looped, effectively creates the sequence "0, 1, 1, 2, 3, 5, 8, 13, 21, 34", as seen in the oport row below:
No extensions this week because it's high time I started Project 8. Sorry!
Thanks to: Melody, Professor Maxwell, Tatsuya, Bumblebee, and anyone else who may have helped me through this long, difficult journey.