Skip to end of metadata
Go to start of metadata

You are viewing an old version of this page. View the current version.

Compare with Current View Page History

« Previous Version 14 Next »

For this week's [very long] project, we built a CPU using the provided CPU design template. The CPU imported data from a ROM, a RAM, and an ALU. 
Tasks 1-3 were to make a project in quartus, then download the provided MIF files for the ROM and RAM. This was done in the same manner as in the last project.

Task 4 defined the signals that we had to use in our top level file, which I called "Project7", in accordance with my "Project#" theme. We wanted a clock, a reset button, and all the register outputs to be included so we could see them in the gtkwaves to come.






The last task was to make the fibonacci sequence as a gtkwave simulation. This meant making an MIF file to give instructions, which was fairly straightforward (except the part where I spent literally 9 hours trying to find my mistake, which turned out to be a colon instead of a semicolon in my MIF...). My logic for this is shown below:

As you can see, I use RA and RB as the indicators for what I want to add. RC is the counter that has RD (which is always 1) subtracted from it each round in the loop, meaning it goes from 10 to 0, and when it's 0, the loop stops, which is how we get the first ten numbers only. The loop is to have the sum of RA and RB get put into RE, then output unless RC reaches 0. Then, RB is passed on to RA and RE is passed on to RB, which, when looped, effectively creates the sequence "0, 1, 1, 2, 3, 5, 8, 13, 21, 34", as seen in the oport row below:

No extensions this week because it's high time I started Project 8. Sorry!

Thanks to: Melody, Professor Maxwell, Tatsuya, Bumblebee, and anyone else who may have helped me through this long, difficult journey.

  • No labels