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1. Summary

In the project, I implemented a reaction timer with sequential digital circuits. I used 7-segment display drivers from the last project and built a timer state machine. I worked with multiple VHDL files and learned to make processes with case statements and to write component and port map statements.

2. Tasks

My top-level file is called reaction. The circuit has a timer, a reset, a start, and a react inputs and three outputs–time in ms and two signals that control the red and green LEDs.

I created a new VHDL file timer that implements a Moore state machine.

My state machine has three states–sIdle, sWait, and sCount.

 

My final circuit design is shown below.

 

Testing using the board:

reaction timer.mp4

The pushbuttons from the leftmost to right control 'start,' 'react,' and 'reset' respectively.

The circuit begins with two digits displaying 0s. When the user hits 'start,' a red LED lights up and the circuit waits for a while. Then a green LED lights up and the timer starts counting, showing the count on the two digits. When the user hits the reaction button, the count freezes.

 

If the user hits the reaction button before the green LED lights up, the counter should show FF and the system should go back to the idle state.

FF.mp4

 

3. Extensions

1) Use a VHDL for your top level file and use component and port map statements to connect the hex driver and state machine circuits.

In my VHDL file reaction.vhd, I used components–SevenSegDriver and timer and added signals. The architecture rtl of reaction makes specific instances of SevenSegDriver and timer through the component instantiations labeled u1, u2, and u3. The port maps associate the signals with ports on the component SevenSegDriver.


Testing using the board:

reaction_VHDL_test.mp4

The behavior is the same as using a bdf file to test.

 

2) Write a testbench VHDL program for your circuit and simulate it using ghdl.

I used the brighttest.vhd file as a template to write my testbench VHDL file where I assigned timed signals to 'start,' 'react,' 'reset' to create specific patterns.


Testing using GTKWave:

Initially, the start, react, and reset buttons are all 1s. When the 'start' button is pressed (which is 0), the red LED becomes 1 (lights up). After a certain amount of time, the red LED switches to a green LED, so the redLED signal becomes 0 and greenLED becomes 1. When the user hits 'react', the green LED lights off (0).

 

3) Make it a game for two players, with two reaction buttons, and see who is faster.

For this extension, I made two timers–timer1 and timer2 to record the two players' reaction times separately so that the two values could display simultaneously on 7-segment displays.

I wrote a new VHDL file twoPlayers that have four instances of SevenSegDriver and instances of timer1 and timer2.

 

Testing using the board:

twoPlayers.mp4

The leftmost button is 'start'. The second and third buttons control player1's and player2's 'react'. The rightmost is the 'reset' button. 

The corresponding digits show up immediately after a player presses their react button. 

 

4) Add the ability to keep track of the shortest reaction time. Display the fastest reaction time on the other two digits, and enable the ability to clear it.

In my timer, I added a clear input that can reset the fastest time to its initial value which is displayed as "FF." I also added an output stTime that represents the shortest time. I used a signal shortest to temporarily store the shortest time for comparing it with the current time and updating the shortest time when needed.

In the process, I added an elsif statement that resets 'shortest' when 'clear' is pressed.

 

Testing with the board:

shortestTime.mp4

The leftmost two digits display the shortest reaction time and the next two digits display the current reaction time.

The buttons from left to right are 'start,' react',' 'reset,' and 'clear.' 

'Reset' resets the current reaction time displayed on the rightmost two digits while 'clear' clears the shortest reaction time displayed on the leftmost two digits.

4. Reflection

The project familiarized me with writing code in VHDL as an efficient way to design my circuits. It was more challenging than using gate-level design since it is more abstract. Additionally, I learned to implement a Moore state machine.

5. Credit

Mike Zheng

Ethan Seal

Max Abramson

Di Luo

Bruce Maxwell

https://www.doulos.com/knowhow/vhdl_designers_guide/components_and_port_maps/

 

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