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1. Summary

In this project, I practiced creating truth tables, Karnaugh maps and using basic digital design components like logic gates. I used Quartus to generate digital logic designs for a prime number circuit and a traffic light circuit. To test my designs, I used a simulation tool–GTKWave. The simulation results were as expected.

2. Tasks

1) Prime Numbers

For task 1, I created a circuit with 4 inputs. The circuit should output a 1 if the input is a prime number and 0 otherwise.

The largest number I can represent with 4 bits is 15 in decimal notation. The first few prime numbers are 2, 3, 5, 7, 11, 13. According to this, I drew a K-map.

After circling the 1s, I derived a Boolean expression based on the K-map:

Y = A'B'C + BC'D + (A ⊕ B)CD

Final Circuit Design:

For testing, I modified the testbench file originally written by Professor Maxwell.

And then I used GTKWave to simulate the result.

2) Traffic Light

For task 2, I created a circuit that has two components.

One is a counter with two inputs–a clock and a reset button.

The output of the counter is a bus with four values.

The second part of the circuit is a combinational circuit that controls the six lights of a 4-way traffic light.

I created a truth table based on the given information, as shown below.

A, B, C, D are inputs and NSR, EWR, NSY, EWY, NSG, EWG are outputs. 

From the truth table, I created a K-map for each output and simplified Boolean expressions accordingly.

Next, I drew circuits in Quartus, as shown below.

I tested the circuits using GHDL. First of all, I replaced my lpm_counter with the new counter. 

Then I modified the clockbench file. 

Finally, I simulated the circuits using GTKWave.

3. Extensions

1) Sometimes, it is more efficient to design the inverse circuit (it outputs 1 for all zeros and 0 for all ones) and invert the output. Explore whether this is the case for one or more of the circuits in this lab.


For my first extension, I converted all 0s to 1s and all 1s to 0s in a new K-map.

Next, I designed the inverse circuits of the prime numbers circuit and then inverted the output.

For the prime numbers circuit, I used 8 gates, including an XOR gate which contributes to efficiency.

For its inverse circuit, I also used 8 gates. It is hard to say which implementation is more efficient. 


The output looks the same.



I also inverted the traffic light circuits.

Firstly, I drew 6 inverted K-maps and derived minimized Boolean expressions accordingly.

From the expressions, we can see that they are simpler than their counterparts above.


The final circuit looks like this:


In the traffic light circuits, there are 30 gates in total.

In the inverse circuits, there are 17 gates in total, almost halved. One of the reasons is that I used "bubble pushing" to reduce the number of inverters.

The implementation was much easier using fewer gates.




2) Pick a different (but simple) function, then go through the design process and implement the circuit.

For my second extension, I chose a sequence: 0, 1, 3 , 5 , 9, 11, 14 , ... which is about the number of comparisons needed to sort n elements by list merging.

I created a truth table and a K-map, as shown below.

The final circuit:


3) Extend the prime numbers circuit to 5 bits.

For my third extension, I extended the prime numbers circuit to 5 bits. A list of prime numbers up to 31 includes 2, 3, 5, 7, 11, 13, 17, 19, 23, 29, and 31. According to this, I drew a truth table and a K-map.

Boolean Expression: Y = A’C’DE + A’B’C’D + AB’C’E + A’B’CE + BCD’E + ACDE

The final circuit:

Since it has 5 inputs–A. B, C, D, E, I modified my testbench.vhd.


4) Figure out how to use an FPGA board to test your circuits in addition to doing the simulation. Show the traffic light outputs on the board LEDs.


For my last extension, I used a board to test my traffic light circuits.


I used an lpm_counter and assigned the pin IDs to keys and LEDs.

Instead of using a toggle switch, I changed to use key[3] as inputs and key[0] as a reset button.

The 6 LEDs(4 red lights, 2 green lights) represent NSR, EWR, NSY, EWY, NSG, EWG respectively, from left to right.

A video of testing is shown below.

4. Reflection

At the end of the project, I learned to use Quartus and GTKWave to generate and simulate my designs. I also practiced Boolean algebra, minimizing, creating truth tables and K-maps. Additionally, I got more familiar with decimal-binary conversion. The most challenging part of the project was to modify the VHDL files, especially the clockbench file.

5. Credit

I would like to thank Di Luo, Hanna Gao, Zixuan Wang, Mike Zheng, Ethan Seal, Max Abramson for help.